1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices. More particularly, this invention relates to flash Electrical Erasable and Programmable Read Only Memories (EEPROMs).
2. Description of the Related Art
Great attention has recently been paid to non-volatile semiconductor memories, such as Ferro-electric Random Access Memories, Erasable and Programmable Read Only Memories (EPROMs) and EEPROMs. As is well known in the art, EPROMs and EEPROMs use floating gates for storing charges that define stored data and control gates for detecting a change in the threshold voltages based on the presence or absence of charges. In addition, EEPROMs include flash EEPROMs that are capable of performing data erasures for all memory storage areas or a plurality of data erasures for selected block storage areas. In general, there are two types of memory cells in a flash EEPROM: one is a split gate type and the other is a stack gate type. International Patent Publication WO92/18980 and U.S. Pat. No. 5,029,130 disclose a split gate flash EEPROM.
In flash EEPROMs, efforts have been made to ensure a multi-value storage operation. The multi-value storage operation generally stores data having three or more values as well as data having two values indicating an erased state and a written state, (i.e., the storage of 1-bit data in one memory cell).
FIG. 1 is a characteristic graph showing the relationship between the cell current that flows in split gate memory cells and the electric potential of a floating gate (hereinafter frequently referred to as "floating gate potential") in each memory cell. In the figure, the floating gate potential indicates the electric potential of the floating gate with respect to the source in each memory cell and is closely associated with the cell current. As apparent from this graph, multivalue data of, for example, four values ("00", "01", "10" and "11") can be stored in each memory cell by associating the individual ranges of a specific current value Id with the individual values of the multivalue data.
In a specific range of the floating gate potential (+0.5 to +2.5 V), the cell current value Id shows a relatively large change. Therefore, the cell current value Id is primarily associated with the floating gate potential Vfg, thus permitting the individual values of multivalue data to be respectively associated with the individual ranges of a specific cell current value Id. When the floating gate potential is less than +0.5 V or equal to or greater than +3.5 V, the cell current is held at a substantially constant value, thus disabling the association of the data values with the cell current values.
FIG. 2 is a characteristic graph showing the relationship between the cell current that flows in stacked gate memory cells and the electric potential of a floating gate in each memory cell. In this type of memory cell, when the floating gate potential Vfg is less than the threshold voltage of the memory cells (about +1 V), the cell current value Id shows zero. When the floating gate potential exceeds the threshold voltage, the cell current value Id is positively proportional to the floating gate potential Vfg, so that multivalue data can be stored in the memory cells.
When the floating gate potential is less than +1 V, however, the cell current value becomes substantially constant, so that the data values can no longer be associated with the cell current values. When the supply voltage is +5 V and the floating gate potential is +6 V or greater, the stacked gate memory cells would suffer the inherent problem of excess erasure, which is undesirable for storage of multivalue data. This excess erasure occurs as charges are excessively drained from the floating gate in an erase mode. Any excessively erased memory cell is turned on even in a standby mode, permitting the flow of the cell current. Consequently, this increases the power consumption. That is, even though a predetermined voltage (0 V) is applied to the control gate of that excessively erased memory cell to turn it off in the standby mode, the channel, or the memory cell, is turned on. Further, even though a voltage of about +5 V is applied to the control gate in an operation of reading the excessively erased memory cell, the electric potential of the floating gate that is capacitively coupled to that control gate is pulled up to or above +6 V. In other words, the value obtained by subtracting the supply voltage V.sub.cc from the floating gate potential Vfg for the excessively erased memory cell exceeds the threshold voltage Vth (i.e., Vfg-V.sub.cc &gt;Vth).
To prevent a data write error in the writing operation or a read error in the reading operation, it is preferable that the individual ranges of the floating gate potential and the cell current value associated with the individual values of multivalue data should have enough margin. In flash EEPROMs, which use split gate memory cells and stacked gate memory cells, however, the suitable cell current values for storing multivalue data are limited to certain ranges due to the reasons given above, making it difficult to ensure such sufficient margin.
In split gate memory cells, for example, the range of the cell current value associated with each data value is 40 .mu.A, the range of the floating gate potential for the data value of "10" is 0.5 V, and the range of the floating gate potential for the data value of "01" is 1 V. In stacked gate memory cells, the range of the cell current value associated with each data value is 40 .mu.A, and the range of the floating gate potential for each data value is 1.25 V.
As the individual ranges of the floating gate potential are relatively narrow, it is difficult to ensure a sufficient margin to accurately set the floating gate potential in the writing operation. As the individual ranges of the cell current value are relatively narrow, it is difficult to ensure a sufficient margin to accurately read the cell current value in the reading operation.
As the number of multivalues increases to eight or sixteen, the individual ranges of the floating gate potential and the cell current value for individual data values become narrower as compared with the case of four values, and thus achieving a sufficient margin becomes more difficult.
Japanese Unexamined Patent Publication No. 7-29383 discloses a ROM from which multivalue data is read by performing the reading operation as separate tasks while changing the voltage to be applied to the word lines. When different multivalue data are stored in a plurality of memory cells connected to a single word line in such a ROM, the reading operation must be performed for each multivalue data in order to read data from those memory cells. In other words, a reading operation must be performed for each of the different multivalue data. Further, while this reading technique can be adapted to a ROM, it is not certain that the reading technique can be adapted to reading and writing data from and to a flash EEPROM.